000			01525cam^a2200361^a^4500
001			UDM01000150399
003			UDM
005			20210531140942.0
008			090613s2010^^^^maua^^^^^b^^^^001^0^eng^d
020			_a0321547993
020			_a9780321547996
082	0	4	_a621.3815 _bB911d 2010
100	1		_9180459 _aBrunvand, Erik, _eautor
245	1	0	_aDigital VLSI chip design with Cadence and Synopsys CAD tools / _cErik Brunvand.
264	3	1	_aBoston : _bAddison-Wesley, _cc2010.
300			_axvi, 571 páginas : _bilustraciones ; _c24 cm.
336			_atexto _btxt _2rdacontent
337			_ano mediado _bn _2rdamedia
338			_avolumen _bnc _2rdacarrier
504			_aInluye bibliografía (p. [565]-566).
505	0		_aIntroduction -- Cadence DFII and ICFB -- Composer schematic capture -- Verilog simulation -- Virtuoso layout editor -- Standard cell design template -- Spectre analog simulator -- Cell characterization -- Verilog synthesis -- Abstract generation -- SOC encounter place and route -- Chip assembly -- Design example -- Appendix A: Tool and setup scripts -- Appendix B: Scripts to drive the tools -- Appendix C: Technology and cell libraries.
650	1	4	_95185 _aCircuitos integrados.
942			_2ddc _cGEN
991			_aELE _aPR15 _aLópez de la Fuente Martha Salomé
997			_aMLOPEZ _b00 _c20150805 _lUDM01 _h1455
998			_aSAMANTHA _b00 _c20150813 _lUDM01 _h1718
999			_c138038 _d138038
900			_aEYR
900			_aFME
900			_aMYM
900			_aDI
900			_aTC