TY  - BOOK
AU  - Brunvand,Erik
TI  - Digital VLSI chip design with Cadence and Synopsys CAD tools
SN  - 0321547993
U1  - 621.3815 
PY  - 2010///
CY  - Boston
PB  - Addison-Wesley
KW  - Circuitos integrados
N1  - Inluye bibliografía (p. [565]-566); Introduction -- Cadence DFII and ICFB -- Composer schematic capture -- Verilog simulation -- Virtuoso layout editor -- Standard cell design template -- Spectre analog simulator -- Cell characterization -- Verilog synthesis -- Abstract generation -- SOC encounter place and route -- Chip assembly -- Design example -- Appendix A: Tool and setup scripts -- Appendix B: Scripts to drive the tools -- Appendix C: Technology and cell libraries
ER  -