Digital integrated circuits : a design perspective / Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolić.
Tipo de material:
TextoSeries Prentice Hall electronics and VLSI series | Prentice Hall electronics and VLSI seriesEditor: Upper Saddle River, N.J. : Pearson Education, c2003Edición: 2nd edDescripción: xxii, 761 páginas : ilustraciones ; 24 cmTipo de contenido: - texto
- no mediado
- volumen
- 0130909963
- 0131207644
- 9780130909961
- 9780131207646
- 621.395 R112d 2003
| Tipo de ítem | Biblioteca actual | Colección | Signatura topográfica | Estado | Notas | Fecha de vencimiento | Código de barras | Reserva de ítems | |
|---|---|---|---|---|---|---|---|---|---|
| Libro | Biblioteca Central | Colección General | 621.395 R112d 2003 (Navegar estantería(Abre debajo)) | Disponible | GEN | 33409002831885 |
Navegando Biblioteca Central estanterías, Colección: Colección General Cerrar el navegador de estanterías (Oculta el navegador de estanterías)
|
|
|
|
|
|
|
||
| 621.395 N149i 1975 An introduction to computer logic / | 621.395 O61 2006 Op Amp applications handbook / | 621.395 P372c 2010 Circuit design and simulation with VHDL / | 621.395 R112d 2003 Digital integrated circuits : a design perspective / | 621.395 R696f 2017 FPGAs : fundamentals, advanced features, and applications in industrial electronics / | 621.395 R845f 2010 Fundamentals of logic design / | 621.395 T355i 1987 Interface circuits data book. |
Incluye bibliografía.
_ Pt. 1. Fabrics -- Ch. 1. Introduction -- Ch. 2. Manufacturing Process -- Design Methodology Insert A: IC LAYOUT -- Ch. 3. Devices -- Design Methodology Insert B: Circuit Simulation -- Ch. 4. Wire -- Pt. 2. Circuit Perspective -- Ch. 5. CMOS Inverter -- Ch. 6. Designing Combinational Logic Gates in CMOS -- Design Methodology Insert C: How to Simulate Complex Logic Circuits -- Design Methodology Insert D: Layout Techniques for Complex Gates -- Ch. 7. Designing Sequential Logic Circuits -- Pt. 3. System Perspective -- Ch. 8. Implementation Strategies for Digital ICS -- Design Methodology Insert E: Characterizing Logic and Sequential Cells -- Design Methodology Insert F: Design Synthesis -- Ch. 9. Coping with Interconnect -- Ch. 10. Timing Issues in Digital Circuits -- Design Methodology Insert G: Design Verification -- Ch. 11. Designing Arithmetic Building Blocks -- Ch. 12. Designing Memory and Array Structures -- Design Methodology Insert H: Validation and Test of Manufactured Circuits.
No hay comentarios en este titulo.